Field-programmable gate arrays are a particular type of programmable device that provides functional flexibility to the user. As opposed to an application-specific integrated circuit (ASIC) or other similar device in which the functionality is “hard-wired” in the device, an FPGA allows a user to program the device to support a relatively wide range of functionality. One of the main advantages of FPGAs over ASICs is that a single FPGA hardware design can provide user-programmable functionality to support many different applications, while an ASIC is limited to the particular functions that are hard-wired into the device at the time of fabrication.
In order to communicate with other components, an FPGA must be able to transmit outgoing signals to and/or receive incoming signals from those other components. There are many different signaling standards in use today that define protocols for signal communications between components. For example, different signaling standards may rely on symmetric or non-symmetric differential or complementary signaling having different sets of voltage levels corresponding to data true, data complement, and the intermediate common-mode voltage.
For purposes of this specification, complementary signaling corresponds to signaling whose DC specifications correspond to full-swing (i.e., rail-to-rail) signaling between a high power-supply voltage Vdd and a low power-supply voltage Vss, where, under DC conditions, a data value of 1 corresponds to Vdd appearing at a true I/O pad and Vss appearing at a complement I/O pad, while a data value of 0 corresponds to Vss appearing at the true pad and Vdd appearing at the complement pad. Differential signaling, on the other hand, corresponds to reduced-swing signaling in which, under DC conditions, the high and low voltage levels (Voh and Vol) appearing at the true and complement pads for data 1 and data 0 fall between the power-supply voltages Vdd and Vss. Thus, assuming DC conditions, in complementary signaling, Vdd=Voh>Vol=Vss, while, in differential signaling, Vdd>Voh>Vol>Vss. Note that, under high-speed AC conditions, the Voh and Vol levels of complementary signaling may fail to reach the full-swing, rail-to-rail signal levels Vdd and Vss.
Symmetric signaling refers to signaling in which the midpoint between the high and low voltage levels Voh and Vol (e.g., the common-mode voltage Vcm) is the same as the midpoint between the high and low power-supply voltages Vdd and Vss, while non-symmetric signaling refers to signaling in which Vcm is not midway between Vdd and Vss (or, in another possible type of non-symmetry, not midway between Vdd and Vss). In general, both complementary and differential signaling can be either symmetric or non-symmetric.
A particular signal-processing system might conform to a particular signaling standard for its inter-component communications. In that case, all of the components in the system would ideally be compatible with that particular signaling standard so that all inter-component communications within the system would conform to that signaling standard.
In the past, an FPGA would be designed to operate in systems that conform to a particular signaling standard. Such an FPGA would be able to transmit and/or receive signals conforming to that particular signaling standard. In order for that same FPGA to be configured to operate in a system that conforms to some other signaling standard, additional hardware, external to the FPGA (e.g., a board-level discrete device), would have to be provided in order to convert (1) incoming signals (i.e., signals transmitted to the FPGA from other system components) from the system's signaling standard to the different signaling standard supported by the FPGA and (2) outgoing signals (i.e., signals transmitted from the FPGA and intended for other system components) from the FPGA's signaling standard to the system's different signaling standard. Alternatively, a different FPGA would have to be designed to support the system's different signaling standard.